Large counters are not as simple as it may seem.
A simple increment counter with a synchronous reset can be described as follow (Code-1)
if rising_edge(CLK) then
if (RST = '1') then
ao_i <= (others => '0');
else
if STR = '1' then
ao_i <= AI;
else
ao_i <= ao_i + 1;
end if;
end if;
end if;
if (RST = '1') then
ao_i <= (others => '0');
else
if STR = '1' then
ao_i <= AI;
else
ao_i <= ao_i + 1;
end if;
end if;
end if;
But the counting process can be divided into chunks of appropriate counting size. Our example (Code 2) has 16 bits wide counting parts. This improve much timing closure in the design
if rising_edge(CLK) then
if (RST = '1') then
ao_i <= (others => '0');
else
if STR = '1' then
ao_i <= AI;
else
for idx in 0 to G_SIZE/16-1 loop
if idx > 0 then
if cycnt(idx-1) = '1' then
ao_i((idx+1)*16-1 downto idx*16) <= ao_i((idx+1)*16-1 downto idx*16) + 1;
end if;
else
ao_i((idx+1)*16-1 downto idx*16) <= ao_i((idx+1)*16-1 downto idx*16) + 1;
end if;
if ao_i((idx+1)*16-1 downto idx*16) = X"FFF"&"1110" then
cycnt(idx) <= '1';
else
cycnt(idx) <= '0';
end if;
end loop;
end if;
end if;
end if;
if (RST = '1') then
ao_i <= (others => '0');
else
if STR = '1' then
ao_i <= AI;
else
for idx in 0 to G_SIZE/16-1 loop
if idx > 0 then
if cycnt(idx-1) = '1' then
ao_i((idx+1)*16-1 downto idx*16) <= ao_i((idx+1)*16-1 downto idx*16) + 1;
end if;
else
ao_i((idx+1)*16-1 downto idx*16) <= ao_i((idx+1)*16-1 downto idx*16) + 1;
end if;
if ao_i((idx+1)*16-1 downto idx*16) = X"FFF"&"1110" then
cycnt(idx) <= '1';
else
cycnt(idx) <= '0';
end if;
end loop;
end if;
end if;
end if;
Below table presents our synthesis results for classic counters
| Technology | Counter size | Resources LUT as Logic | Path Delay [ns] |
| Virtex-7 vx690 speed -2 | 16 32 64 128 256 | 31 64 125 255 512 | 1.121 1.40 1.83 2.69 4.31 |
| Virtex Ultrascale vu440 speed -2 | 16 32 64 128 256 | 40 64 126 256 511 | 1.085 1.209 1.369 1.791 2.563 |
| Virtex UltrascalePlus vu9p speed -2 | 16 32 64 128 256 | 40 64 126 256 511 | 0.743 0.791 0.923 1.249 1.879 |
Improved counters (Code-2) have about 30% – 80% better synthesis results
| Technology | Counter size | Resources LUT as Logic | Path Delay [ns] |
| Virtex-7 vx690 speed -2 | 16 32 64 128 256 | 31 69 141 284 571 | 1.121 1.481 1.506 1.657 1.635 |
| Virtex Ultrascale vu440 speed -2 | 16 32 64 128 256 | 40 82 176 338 669 | 1.085 1.024 1.115 1.297 1.307 |
| Virtex UltrascalePlus vu9p speed -2 | 16 32 64 128 256 | 38 80 160 329 667 | 0.743 0.679 0.851 0.717 0.923 |
The results were taken for XilinxR Vivado 2019.2.1