ISKRA Technical Projects and ConsultationsA few months ago I have came across an interesting implementation problem. Xilinx Vivado IDE has a curious optimization strategy. This occurs in a situation where each module of a design is in a different CDC (clock domain cross) zone. Sample diagram of such HDL design is here: After Xilinx Vivado IDE synthesis everything was […]
Large counters are not as simple as it may seem. A simple increment counter with a synchronous reset can be described as follow (Code-1) But the counting process can be divided into chunks of appropriate counting size. Our example (Code 2) has 16 bits wide counting parts. This improve much timing closure in the design […]
One hot selector, G_LEN inputs and single output. G_SIZE is width of the data vector. G_LEN is the number of vectors to select. Technology ArchitectureG_SIZE x G_LEN Resources LUT as Logic Path Delay[ns] Virtex-7vx690 8 x 168 x 6432 x 1632 x 64 762882931090 1.6132.1211.6802.610 Virtex Ultrascalevu440 8 x 168 x 6432 x 1632 x […]